tm
TE
CH
•
T431616D/E
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential
Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length
of 4 and 8.
A3
0
1
Addressing Mode
Sequential
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which
is input to the device. The internal column address is varied by the Burst Length as shown in the
following table. When the value of column address, (n + m), in the table is larger than 255, only
the least significant 8 bits are effective.
Data n
Column Address
0
n
1
n+1
2
n+2
3
n+3
4
n+4
5
n+5
6
n+6
7
n+7
-
-
255
n+255
256
n
257
n+1
-
-
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
Data n
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
•
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
Column Address
A4
A4
A4
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A1
A1
A0
A0#
4 words
8 words
Burst Length
A1# A0
A1# A0#
A0
A0#
A2# A1
A2# A1
A2# A1# A0
A2# A1# A0#
CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field.
t
CAC
(min)
≤
CAS# Latency X t
CK
A6
0
0
0
0
1
A5
0
0
1
1
X
A4
0
1
0
1
X
CAS# Latency
Reserved
1 clock
2 clocks
3 clocks
Reserved
TM Technology Inc. reserves the right
P. 13
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
