TE
tmCH
T436416A
PIN DESCRIPTION
INPUT FUNCTION
PIN
NAME
CLK
System Clock
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CS
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with RAS low.
CKE
Clock Enable
A0 ~ A11
Address
BA0 ~ BA1
Bank Select Address
Row Address Strobe
RAS
CAS
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Column Address Strobe
Write Enable
Enables column access .
Enables write operation and row precharge.
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data Input/Output
Mask
L(U)DQM
DQ0 ~ DQ15
VDD/VSS
Data Input/Output
Power Supply/Ground
Data Output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
Power/Ground
No
This pin is recommended to be left No Connection on the device.
N.C/RFU
Connection/Reserved
for Future Use
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
