TE
tmCH
T436416A
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
Speed Version
-7 -7.5 -8 -10
Parameter
Symbol
Unit Note
-6
Row active to row active delay
RAS to CAS delay
12
14
18
20
42
15
18
20
16
20
20
48
20
20
20
50
ns
ns
ns
1
1
1
1
tRRD
(min)
(min)
16
18
42
tRCD
tRP
Row precharge time
(min)
45
100K
65
1
2
1
1
1
1
ns
ns
ns
CLK
CLK
CLK
CLK
tRAS
(min)
(max)
(min)
Row active time
tRAS
Row cycle time
60
63
68
70
1
2
2
2
3
tRC
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
tCDL
tRDL
tBDL
tCCD
(min)
(min)
(min)
(min)
Col. Address to col. Address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
