CHA2095a
The circuit schematic is given below :
36-40GHz Low Noise Amplifier
Typical Bias Tuning for Low Noise Operation
Vd
Vd
100
IN
100
50
50
OUT
Vg 1,2
Vg 3,4
For low noise operation, a separate access to the gate voltages of the two first stages ( Vg1,2 ), and
of the two last stage ( Vg3,4 ) is provided. Nominal bias is obtained for a typical current of 60 mA for
the output stages and 30 mA for the two first stages ( 90 mA for the amplifier ).
The first step to bias the amplifier is to tune Vg1,2 = -1V, and Vg3,4 to drive 60 mA for the full
amplifier. Then Vg1,2 is increased to obtain 90 mA of current through the amplifier. A fine tuning of
the noise figure may be obtained by modifying the Vg1,2 bias voltage, but keeping the previous value
for Vg3,4.
It is possible to reduce the total DC current by biasing Vg3,4 to a more negative value. The
consequences will be a reduction of gain and of the output power capabilities of the amplifier.
Vd could be adjust in such a way that the Vds ( Drain to Source voltage of the internal transistor ) is
kept below 3.5V, knowing that all the transistor have the same size, and with the given resistors.
Ordering Information
Chip form
:
CHA2095a99F/00
Information furnished is believed to be accurate and reliable. However
United Monolithic Semiconductors
S.A.S.
assumes no responsability for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of
United Monolithic Semiconductors S.A.S..
Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied.
United Monolithic Semiconductors S.A.S.
products are not authorised for
Ref. : DSCHA20958147
6/7
Specifications subject to change without notice
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