VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
Figure 7: Parametric Measurement Information
1.0625 Gbits/sec Fibre
Channel Transceiver
Serial Input Rise and Fall Time
80%
20%
TTL Input and Output Rise and Fall Time
V
ih(min)
V
il(max)
T
r
T
f
T
r
T
f
Receiver Input Eye Diagram Jitter Tolerance Mask
Bit Time
Amplitude
Total jitter tolerance is
0.7UI, according to
Fibre Channel 4.3 Annex J
Eye Width%
Parametric Test Load Circuit
Serial Output Load
TTL A.C. Output Load
Z
0
= 75Ω
75Ω
10 pF
V
DD
– 2.0V
G52148-0, Rev. 4.3
3/4/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9