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VSC7135QN 参数 Datasheet PDF下载

VSC7135QN图片预览
型号: VSC7135QN
PDF下载: 下载PDF文件 查看货源
内容描述: 1.25Gbits /秒的千兆以太网收发器 [1.25Gbits/sec Gigabit Ethernet Transceiver]
分类和应用: 网络接口电信集成电路电信电路以太网以太网:16GBASE-T
文件页数/大小: 16 页 / 125 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7135
Features
• Gigabit Ethernet Transceiver @ 1.25Gb/s
• Compliant to IEEE 802.3Z PMA
• TTL Interface Compatible to PMA-TBI
• Monolithic Clock Synthesis and Clock
Recovery - No External Components
• 125MHz TTL Reference Clock
1.25Gbits/sec
Gigabit Ethernet Transceiver
• Low Power Operation - 700 mW
• Suitable for Both Coaxial or Optical Link
Applications
• 64 Pin, 14mm or 10mm Standard PQFP
• Single +3.3V Supply
General Description
The VSC7135 is a 1.25Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-X applica-
tions. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it
onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135
also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it
onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and
detects “Comma” characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate trans-
mit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and
require no external components.
VSC7135 Block Diagram
EWRAP
R0:9
10
QD
Serial to
Parallel
÷
10
Retimed
Data
Recovered
Clock
QD
Clock
Recovery
2:1
RX+
RX-
RCLK
RCLKN
Frame
Logic
÷
20
Comma
Detect
Resync
COM_DET
EN_CDET
10
T0:9
DQ
Parallel
to Serial
Serial Data
Synthesized
Clock
DQ
TX+
TX-
REFCLK
PLL Clock
Multiply
G52146-0, Rev. 4.0
5/28/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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