VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7135
1.25Gbits/sec
Gigabit Ethernet Transceiver
ing parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In
order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output
register at a point nominally midway between the transition edges of RCLK and RCLKN.
If serial input data is not present, or does not meet the required baud rate, the VSC7135 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output
frequency under these circumstances may differ from their expected frequency by no more than +1%.
Word Alignment
The VSC7135 provides 7-bit comma character recognition and data word alignment. Word synchronization
is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7135 constantly examines
the serial data for the presence of the “Comma” character. This pattern is “0011111XXX”, where the leading
zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded
data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5
and K28.7, which are defined specifically for synchronization purposes. Improper alignment of the comma
character is defined as any of the following conditions:
1) The comma is not aligned within a the 10-bit transmission character such that T0...T6 = “0011111”
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.
When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in
such a manner that the comma character is aligned properly in R0:9. This results in proper character and half-
word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern,
some data which would have been presented on the parallel output port may be lost. However, the synchroniza-
tion character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the
current alignment of the serial data is maintained indefinitely, regardless of data pattern.
On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the
parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma char-
acter and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that
it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for syn-
chronization are given in Figure 3 and Figure 4. Figure 3 shows the case when a comma character is detected
and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma
character on R0:9. Figure 4 shows the case where the K28.5 is detected, but it is out of phase and a change in
the output data alignment is required. Note that up to three characters prior to the comma character may be cor-
rupted by the realignment process.
G52146-0, Rev. 4.0
5/28/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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