VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7135
AC Characteristics
Figure 4: Transmit Timing Waveforms
1.25Gbits/sec
Gigabit Ethernet Transceiver
REFCLK
T
1
T
2
T0:9
10 Bit Data
Data Valid
Data Valid
Data Valid
Table 1: Transmit AC Characteristics
Parameters
T
1
T
2
T
SDR
,T
SDF
T
LAT
Description
T0:9 Setup time to the rising
edge of REFCLK
T0:9 hold time after the
rising edge of REFCLK
TX+/TX- rise and fall time
Min
1.5
Max
—
Units
ns.
Conditions
Measured between thevalid
data level of T0:9 to the 1.4V
point of REFCLK
1.0
—
—
300
ns.
ps.
20% to 80%, 75 Ohm load to
Vss, Tested on a sample basis
bc = Bit clocks
ns = Nano second
Latentcy from rising edge of
11bc - 1ns
ns.
REFCLK to T0 appearing on
TX+/TX-
Transmitter Output Jitter Allocation
Total data output jitter (p-p)
Serial data output
deterministic jitter (p-p)
—
—
192
80
ps.
ps.
T
J
T
DJ
IEEE 802.3Z Clause 38.68,
tested on a sample basis
IEEE 802.3Z Clause 38.69,
tested on a sample basis
G52146-0, Rev. 4.0
5/28/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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