VIS
T0
T1
T2
CLK
Bank
Col A
ADDRESS
Preliminary
T3
T4
T5
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
T6
T7
T8
Bank(s)
t RP
Bank
Row
COMMAND
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
CAS Iatency = 1
t
CK1
,DQ’s
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
CAS Iatency = 2
t
CK2
,DQ’s
CAS Iatency = 3
t
CK3
,DQ’s
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
Read to Precharge (CAS Latency = 1, 2, 3)
6
Read and AutoPrecharge command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A9 = ”H”, A0-A7 = Column Address,
A8 = Don’t care
)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command can not occur within a time delay of
{t
RP
(min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto pre-
charge function is ignored.
Write command
(RAS = ”H”, CAS = ”L”, WE = ”L”, DSF = “L”, BS = Bank, A9 = ”L”, A0-A7 = Column Address,
A8 = Don’t care
)
The Write command is used to write burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data ele-
ments will be registered on each successive positive clock edge (refer to the following figure). The DQs remains
high-impedance at the end of the burst, unless other command was initiated. The burst length and burst
sequence are determined by the mode register which is already programmed. A full-page burst will continue
until terminated (at the end of the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
7
CLK
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ0 - DQ3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
don’t care
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a
masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the
data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte
basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram.
Document:1G5-0145
Rev.1
Page 10
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
