VIS
T0
T1
T2
CLK
DQM
Preliminary
T3
T4
T5
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
T6
T7
T8
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ’s
DOUT A
0
Must be Hi-Z before
the Write Command
DINB
0
DINB
1
DINB
2
: “H” or “L”
Read to Write interval (Burst Length
°Ÿ
4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
COMMAND
NOP
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
CAS Iatency = 1
t
CK1
,DQ’s
Must be Hi-Z before
the Write Command
DIN A
0
DIN A
1
DIN A
2
DIN A
3
CAS Iatency = 2
t
CK2
,DQ’s
DIN A
0
DIN A
1
DIN A
2
DIN A
3
: “H” or “L”
Read to Write interval (Burst Length
°Ÿ
4, CAS Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
READ A
NOP
NOP
WRITE B
NOP
NOP
NOP
CAS Iatency = 1
t
CK1
,DQ’s
DOUT A
0
Must be Hi-Z before
the Write Command
DIN B
0
DIN B
1
DINB
2
DIN B
3
CAS Iatency = 2
t
CK2
,DQ’s
DIN B
0
DIN B
1
DIN B
2
DIN B
3
: “H” or “L”
Read to Write interval (Burst Length
°Ÿ
4, CAS Latency = 1, 2)
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
Document:1G5-0145
Rev.1
Page 9
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
