EDI2CG472128V
White Electronic Designs
ADVANCED
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92,
9, 94, 12, 96, 10,
93, 8, 91, 5, 88, 3
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with A0 and A1, during burst and wait cycle.
Input
Synchronous
A0-A16
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BW0/ controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1.
BW2# controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.
BW6# controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
107, 106, 23, 22,
109, 108, 25, 24
Input
Synchronous
Input
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
104
19
BWE#
GW#
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent
of the BWE# and BWx# lines and must meet the setup and hold times around the
rising edge of CK.
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Input
Synchronous
101
CK
E1#, E2#,
E3#, E4#
Input
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
98, 15, 99, 14
103
Synchronous
G#
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Input
Address Status Processor: This active LOW input is used to control the internal burst
counter. A HIGH on this pin generates wait cycle (no address advance).
111
27
ADV#
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
Input
Synchronous
ADSP#
Address Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered.
Input
26
17
ADSC#
MODE
Synchronous
A READ or WRITE cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
Input Static
Snooze: These active HIGH inputs put the individual banks in low power
consumption standby mode. For normal operation, this input has to be either
LOW or NC (no connect).
36, 50,
64, 78
ZZ1, ZZ2,
ZZ3, ZZ4
Input
Asynchronous
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
DQ0-63
DQP0-7
Input/Output
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ-32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a
128K x 64, the parity bits need to be tied to VSS through a 10K ohm resistor.
113, 120, 127, 134,
141, 148, 155, 162
Various
Various
Vcc
Vss
Supply
Ground
Core Power supply: +3.3V -5%/+10%
Ground
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
