White Electronic Designs
BURST ADDRESS TABLE (MODE=NC/V
CC
)
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A00
A-A11
A-A10
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A10
A-A01
A-A00
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A10
A-A11
A-A00
EDI2CG472128V
ADVANCED
BURST ADDRESS TABLE (MODE=GND)
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A00
A-A01
A-A10
READ CYCLE TIMING PARAMETERS
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
*TBD
Sym
t
KHKH
t
KHKL
t
KLKH
t
KHQV
t
KHQX1
t
KHQX
t
GLQV
t
GLQX
t
GHQZ
t
AVKH
t
EVKH
t
KHAX
t
KHEX
8.5ns
Min
Max
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
10ns
Min
Max
15
5
5
10
3
4
5
0
5
2.5
2.5
1.0
1.0
12ns
Min
Max
15
5
5
12
3
4
5
0
5
2.5
2.5
1.0
1.0
15ns
Min Max
20
6
6
15
3
4
6
0
5
2.5
2.5
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KHKL
t
KLKH
CK
t
AVKH
Ex#
ADDR
Addr 1
Addr 1
Addr 2
t
KHAX
G#
t
KHQV
GW#
t
KHQX
DQ
Q(Addr 1)
t
KHQZ
Read Cycle
t
GLQV
t
GLQX
Q(Addr 1)
Q(Addr 2)
t
KHQX1
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
