White Electronic Designs
SYNC-BURST READ CYCLE
t
KHKH
t
KHKL
t
KLKH
EDI2CG472128V
ADVANCED
CK
t
SPVKH
t
KHSPX
ADSP#
t
SCVKH
t
KHSCX
ADSC#
t
AVKH
t
KHAX
ADDR
BWx,
GW#
t
EVKH
t
KHEX
Ex#
t
AVVKH
t
KHAVX
ADV#
t
GHQX
G#
t
KHQV
t
GLQV
t
GLQX
DQ
t
GHQZ
t
KHQX
t
KHQX
Read Cycle
Burst Read Cycle
WRITE CYCLE TIMING PARAMETERS
8.5ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
*TBD
10ns
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Max
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
12ns
Max
15ns
Min
20
6
6
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Sym
t
KHKH
t
KHKL
t
KLKH
t
AVKH
t
KHAX
t
EVKH
t
KHEX
t
WVKH
t
KHWX
t
DVKH
t
KHDX
Min
*
*
*
*
*
*
*
*
*
*
*
Max
*
*
*
*
*
*
*
*
*
*
*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
