EDI2DL32256V
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
s
t
KHQV
times of 3.5, 3.8 and 4.0ns
s
166, 150 and 133 MHz clock speed
s
DSP Memory Solution
• Texas Instruments’ TMS320C6201
• Texas Instruments’ TMS320C67x
s
Package:
• 119 pin BGA, JEDEC MO-163
s
3.3V Operating Supply Voltage
s
3.5ns Output Enable access time
s
Single Write Control and Output Enable Lines
s
Single Chip Enable Line
s
56% space savings vs. monolithic TQFPs
s
Multiple VCC and VSS pins
s
Reduced inductance and capacitance
DESCRIPTION
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline
Burst SRAM constructed with two 256Kx16 die mounted on a
multi-layer laminate substrate. The device is packaged in a 119
lead, 14mm by 22mm, BGA. It is available with clock speeds of166,
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing
the user to develop a fast external memory for Texas Instruments’
“C6x”. In Burst Mode data from the first memory location is
available in three clock cycles, while the subsequent data is
available in one clock cycle (3/1/1/1). Subsequent burst ad-
dresses are generated by the TMS320C6x DSP. Individual address
locations can also be read, allowing one memory access in 3 clock
cycles. All synchronous inputs are gated by registers controlled by
a positive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, chip enable (CE\), burst
control input (ADSC\), byte write enables (BW0\ to BW3\) and
Write Enable (BWE\).
Asynchronous inputs include the output enable (OE\), burst mode
control (MODE), and sleep mode control (ZZ). The data outputs
(DQ), enabled by OE\, are also asynchronous.
Address lines and the chip enable are registered with the address
status controller (ADSC\) input pin.
FIG. 1
PIN CONFIGURATION
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
NC
NC
DQ
16
DQ
18
V
DD
DQ
21
DQ
23
V
DD
DQ
31
DQ
29
V
DD
DQ
26
DQ
24
NC
NC
V
DD
1
2
A
NC
A
NC
DQ
17
DQ
19
DQ
20
DQ
22
V
DD
DQ
30
DQ
28
DQ
27
DQ
25
NC
A
NC
NC
2
3
A
A
A
V
SS
V
SS
V
SS
BE
2
\
V
SS
NC
V
SS
BE
3
\
V
SS
V
SS
V
SS
MODE
A
NC
3
4
NC
ADSC\
V
DD
NC
CE\
OE\
NC
NC
V
DD
CLK
NC
BWE\
A
1
A
0
V
DD
A
NC
4
5
A
A
A
V
SS
V
SS
V
SS
BE
1
\
V
SS
NC
V
SS
BE
0
\
V
SS
V
SS
V
SS
NC
A
NC
5
6
A
A
A
NC
DQ
9
DQ
11
DQ
12
DQ
14
V
DD
DQ
6
DQ
4
DQ
3
DQ
1
NC
A
NC
NC
6
7
V
DD
NC
NC
DQ
8
DQ
10
V
DD
DQ
13
DQ
15
V
DD
DQ
7
DQ
5
V
DD
DQ
2
DQ
0
NC
ZZ
V
DD
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
256K X 16
SSRAM
BLOCK DIAGRAM
A
0
-
17
CLK
ADSC\
OE\
BWE\
CE\
MODE
ZZ
BE
0
\
BE
1
\
BE
2
\
BE
3
\
DQ
0
-
7
DQ
8
-
15
DQ
16
-
23
DQ
24
-
31
256K X 16
SSRAM
November 2000, Rev. 1
ECO #13417
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
