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EDI2DL32256V35BC 参数 Datasheet PDF下载

EDI2DL32256V35BC图片预览
型号: EDI2DL32256V35BC
PDF下载: 下载PDF文件 查看货源
内容描述: 256Kx32同步Pipline突发3.3V SRAM [256Kx32 Synchronous Pipline Burst SRAM 3.3V]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 8 页 / 98 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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EDI2DL32256V  
ABSOLUTE MAXIMUM RATINGS*  
RECOMMENDED OPERATING CONDITIONS  
Voltage on Vcc Supply Relative to Vss  
VIN  
-0.5V to 4.6V  
-0.5V to Vcc+0.5V  
-55°C to +110°C  
+110°C  
Description  
Symbol  
VIH  
Min  
2
Max  
Vcc+0.3  
0.7  
Unit  
V
Input High Voltage  
Input Low Voltage  
Supply Voltage  
Storage Temperature  
VIL  
-0.3  
3.135  
V
Junction Temperature  
Power Dissipation  
Vcc  
3.465  
V
3 Watts  
Short Circuit Output Current (per I/O)  
20 mA  
CAPACITANCE  
(f = 1MHz, VIN = VCC or VSS)  
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause  
permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions greater than those indi-  
cated in the operational sections of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect reliability.  
Parameter  
Symbol  
CA  
Max  
Unit  
Address Lines  
Data Lines  
TBD  
TBD  
TBD  
pF  
pF  
pF  
CD/Q  
CC  
Control Lines  
PARTIAL TRUTH TABLE  
Function  
BWE\  
BE0\  
BE1\  
BE2\  
BE\3  
READ  
H
L
L
X
L
L
X
H
L
X
H
L
X
H
L
WRITE one Byte (DQ0-7)  
WRITE all Bytes  
DC ELECTRICAL CHARACTERISTICS  
(f = 1MHz, VIN = VCC or Vss)  
Parameter  
Symbol  
Conditions  
Min  
Max  
Units  
Device Selected; all inputs VIL or VIH;  
cycle time tKC MIN; VCC = MAX; outputs open  
Power Supply Current: Operating  
ICC1  
850  
mA  
Device deselected; VCC = MAX; all inputs ≤  
VSS +0.2 or VCC -0.2; all inputs static;  
CLK frequency = 0  
CMOS Standby  
ISB2  
20  
mA  
Device deselected; all inputs VIL or VIH;  
all inputs static; VCC = MAX; CLK frequency = 0  
TTL Standby  
TTL Standby  
ISB3  
ISB4  
40  
40  
mA  
mA  
Device deselected; all inputs VIL or VIH;  
VCC = MAX; CLK cycle time tCK MIN  
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
ILI  
ILO  
VOH  
VOL  
0V < VIN < VCC  
-2  
-2  
2
2
µA  
µA  
V
Output(s) disabled, 0V VOUT VCC  
IOH = -2.0mA  
2.4  
IOL = 2.0mA  
0.7  
V
AC TEST CIRCUIT  
AC TEST CONDITIONS  
Parameter  
I/O  
Unit  
V
Output  
Z0=50Ω  
Input Pulse Levels  
VSS to 2.5  
1.8  
Input Rise and Fall Times (max)  
Input and Output Timing Levels  
Output Load  
ns  
1.25  
V
50  
See figure, at left  
1 V  
Vt = 125
AC Output Load Equivalent  
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com  
November 2000, Rev. 1  
ECO #13417