EDI2DL32256V
FIG. 5
INTERFACING THE TEXAS INSTRUMENTS TMS320C6201
WITH THE EDI2DL32256V (256Kx32 SSRAM)
EA0-22
A0-17
(NOTE 1)
(NOTE 4)
CE2
CE1
CE0
\
\
\
CE\
ZZ
MODE
NC, Vss, Vcc
(NOTE 2)
BE
BE
BE
BE
3\
2\
1\
0
\
BE3
BE2
BE1
BE0
\
\
\
\
Texas Instruments
TMS320C6201
EDI2DL32256V
SSOE\
OE\
SSADS\
SSADV\
ADSC\
ADV\
SSWE\
CLKOUT1
CLKOUT2
GW\ (NOTE 3)
CLK
ED0-31
DQ0-31
NOTES:
1. Either CE0 or CE2 can be used to enable the device.
2. When the ZZ pin is asserted HIGH, the device will be in CMOS standby mode regardless of the state of any other pins. While in standby mode the device will
take one complete Clock cycle to become active again after a LOW is asserted on the ZZ pin. One possible option for the designer concerned about power is
to tie the ZZ signal to the chip enable they are using for the device. Any time the chip is disabled (by driving the chip enable pin HIGH) the device will go into
standby mode. Standby mode can also be achieved by tying the ZZ pin LOW or allowing it to float and meeting all the signal conditions specified in the data
sheet.
3. Use CLKOUT1 for running the memory at the same clock speed as the C6x. Use CLKOUT2 for running the SBSRAM at one half the clock rate of the C6x.
4. The MODE pin can be tied to Vss (Linear Burst), tied to Vcc (Interleaved Burst) or allowed to float (Interleaved Burst).
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
November 2000, Rev. 1
ECO #13417
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
