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W3H64M72E-ESC 参数 Datasheet PDF下载

W3H64M72E-ESC图片预览
型号: W3H64M72E-ESC
PDF下载: 下载PDF文件 查看货源
内容描述: 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装 [64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 30 页 / 942 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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White Electronic Designs
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
W3H64M72E-XSBX
ADVANCED*
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specified time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA2 BA1 BA0 A13 A12
A11 A10 A9 A8 A7 A6 A5 A4 A3
A2
A1 A0
Address Bus
16 15 14
MRS
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
0
2
out
RDQS DQS# OCD Program
R
TT
Posted CAS#
R
TT
ODS DLL
E12
0
1
Outputs
Enabled
Disabled
E0
E6 E2 Rtt (nominal)
0
0
0
1
0
1
R
TT
disabled
75Ω
150
50Ω
0
1
DLL Ena ble
Enable (Normal)
Disable (Test/Debug)
E11 RDQ S Ena ble
0
1
No
Yes
1
1
E1
0
1
Output Drive Strength
Full strength (18
target)
Reduced strength (40
target)
E10 DQ S# Ena ble
0
1
Enable
Disable
E5 E4 E3 Poste d CA S# A dditive Laten cy (AL)
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
Reserved
Reserved
Reserved
E9 E8 E7
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD Operation
OCD not supported
Reserved
Reserved
Reserved
OCD default state
1
1
0
1
1
1
1
E16 E15 E14
0
0
0
0
0
0
1
1
0
1
0
1
Mo de Regi ster Set
Mode register set (MRS)
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is finished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com