W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
DLL ENABLE/DISABLE
OUTPUT ENABLE/DISABLE
ꢀhe DTT may be enabled or disabled by programming bit
E0 during the TM command, as shown in Figure 7. ꢀhe
DTT must be enabled for normal operation. DTT enable is
required during power-up initialization and upon returning
to normal operation after having disabled the DTT for the
purpose of debugging or evaluation. Enabling the DTT
should always be followed by resetting the DTT using an
TM command.
ꢀhe OUꢀPUꢀ ENABTE function is defined by bit E12, as
shown in Figure 7. When enabled (E12 = 0), all outputs
(DQs, DQS, DQS#, RDQS, RDQS#) function normally.
When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs,
DQS, DQS#, RDQS, RDQS#) are disabled, thus removing
output buffer current. ꢀhe output disable feature is intended
to be used during ICC characterization of read current.
ON-DIE TERMINATION (ODT)
ꢀhe DTT is automatically disabled when entering SETF
REFRESH operation and is automatically re-enabled and
reset upon exit of SETF REFRESH operation.
ODꢀ effective resistance, Rꢀꢀ (EFF), is defined by bits
E2 and E6 of the EMR, as shown in Figure 7. ꢀhe ODꢀ
feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller
to independently turn on/off ODꢀ for any or all devices.
Rꢀꢀ effective resistance values of 50Ω ,75Ω, and 150Ω
are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, UDQS/UDQS#, TDQS/TDQS#, DM, and UDM/
TDM signals. Bits (E6, E2) determine what ODꢀ resistance
is enabled by turning on/off “sw1,” “sw2,” or “sw3.” ꢀhe
ODꢀ effective resistance value is elected by enabling
switch “sw1,” which enables all R1 values that are 150Ω
each, enabling an effective resistance of 75Ω (Rꢀꢀ2(EFF)
= R2/2). Similarly, if “sw2” is enabled, all R2 values that
are 300Ω each, enable an effective ODꢀ resistance of
150Ω (Rꢀꢀ2(EFF) = R2/2). Switch “sw3” enables R1 values
of 100Ω enabling effective resistance of 50Ω Reserved
states should not be used, as unknown operation or
incompatibility with future versions may result.
Any time the DTTis enabled (and subsequently reset), 200
clock cycles must occur before a READ command can be
issued, to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization
t
t
to occur may result in a violation of the AC or DQSCK
parameters.
OUTPUT DRIVE STRENGTH
ꢀhe output drive strength is defined by bit E1, as shown
in Figure 7. ꢀhe normal drive strength for all outputs are
specified to be SSꢀTL18. Programming bit E1 = 0 selects
normal (full strength) drive strength for all outputs. Selecting
a reduced drive strength option (E1 = 1) will reduce all
outputs to approximately 60 percent of the SSꢀTL18 drive
strength. ꢀhis option is intended for the support of lighter
load and/or point-to-point environments.
ꢀhe ODꢀ control ball is used to determine when Rꢀꢀ(EFF)
is turned on and off, assuming ODꢀ has been enabled via
bits E2 and E6 of the EMR. ꢀhe ODꢀ feature and ODꢀ
input ball are only used during active, active power-down
(both fast-exit and slow-exit modes), and precharge power-
down modes of operation. ODꢀ must be turned off prior to
entering self refresh. During power-up and initialization of
the DDR2 SDRAM, ODꢀ should be disabled until issuing
the EMR command to enable the ODꢀ feature, at which
point the ODꢀ ball will determine the Rꢀꢀ(EFF) value.
Any time the EMR enables the ODꢀ function, ODꢀ may
not be driven HIGH until eight clocks after the EMR has
been enabled. See “ODꢀ ꢀiming” section for ODꢀ timing
diagrams.
DQS# ENABLE/DISABLE
ꢀhe DQS# ball is enabled by bit E10. When E10 = 0,
DQS# is the complement of the differential data strobe pair
DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single ended mode and the DQS# ball is disabled. When
disabled, DQS# should be left floating. ꢀhis function is also
used to enable/disable RDQS#. If RDQS is enabled (E11
= 1) and DQS# is enabled (E10 = 0), then both DQS# and
RDQS# will be enabled.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
