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WED2DL32512V35BC 参数 Datasheet PDF下载

WED2DL32512V35BC图片预览
型号: WED2DL32512V35BC
PDF下载: 下载PDF文件 查看货源
内容描述: 512Kx32同步管道突发式SRAM [512Kx32 Synchronous Pipeline Burst SRAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 9 页 / 146 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED2DL32512V
PARTIAL TRUTH TABLE - WRITE COMMANDS
Function
BWE
BWa
BWb
BWc
BWd
Read
H
X
X
X
X
Read
L
H
H
H
H
Write Byte “a”
L
L
H
H
H
Write All Bytes
L
L
L
L
L
NOTE:
Using BWE and BWa through BWd, any one or more bytes may be written.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply relative to V
SS
Voltage on V
DDQ
Supply relative to V
SS
V
IN
(DQx)
V
IN
(Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to +4.6V
-0.5V to V
DDQ
+0.5V
-0.5V to V
DD
+0.5V
-55°C to +125°C
100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Description
Input High (Logic 1)Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Ouptut Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
V
DD
Conditions
Min
2.0
-0.3
Max
V
DD
+0.3
0.8
1.0
1.0
0.4
3.6
V
Units
V
V
mA
mA
V
V
V
Notes
1
1
2
1
1
1
0V
V
IN
V
DD
Output(s) disabled, 0V
V
IN
V
DD
I
OH
= -4.0mA
I
OL
= 8.0mA
3.134
-1.0
-1.0
2.4
3.135
3.6
Isolated Output Buffer SupplyV
DDQ
NOTES:
1. All voltages referenced to Vss (GND).
2. MODE has an internal pull-up, and input leakage =
±10µA.
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
CMOS Standby
TTL Standby
Clock Running
Symbol
I
DD
I
SB2
I
SB3
I
SB4
Conditions
Device selected; All inputs
V
IL
or 3 V
IH
; Cycle time 3 t
KC
MIN;
V
DD
= MAX; Outputs open
Device deselected; V
DD
= MAX; All inputs
V
SS
+ 0.2
or V
DD
- 0.2; All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX; All inputs
V
IL
or V
IH
;
All inputs static; CLD frequency = 0
Device deselected; V
DD
= MAX; All inputs
V
SS
+ 0.2
or V
DD
-0.2; Cycle time 3 t
KC
MIN
Typ
200*
MHz
950
10
20
80
20
40
220
166
MHz
800
20
40
180
150
MHz
740
20
40
160
133
MHz
600
20
40
140
Units
mA
mA
mA
mA
Notes
1,2,3
2,3
2,3
2,3
* Advanced Information
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C and 133MHz.
BGA CAPACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES:
1. This parameter is sampled.
Conditions
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
Symbol
C
I
C
O
C
A
C
CK
Typ
3
4
3
2.5
Max
6
5
5
4
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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