WED2DL32512V
AC CHARACTERISTICS
Symbol
Parameter
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
Output Times
Clock to output valid
Clock to output invalid (2)
Clock to output on Low-Z (2,3,4)
Clock to output in High-Z (2,3,4)
OE to output valid (5)
OE to output in Low-Z (2,3,4)
OE to output in High Z (2,3,4)
Setup Times
Address (6,7)
Address status (ADSC) (6,7)
Write signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip enables (CE) (6,7)
Hold Times
Address (6,7)
Address status (ADSC) (6,7)
Write Signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip Enables (CE) (6,7)
t
AH
t
ADSH
t
WH
t
DH
t
CEH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
t
AS
t
ADSS
t
WS
t
DS
t
CES
1.5
1.5
1.5
1.5
1.5
0
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0
3.0
2.5
0
3.5
1.5
1.5
1.5
1.5
1.5
2.5
1.25
0
3.5
3.5
0
3.8
1.5
1.5
1.5
1.5
1.5
3.5
1.25
0
3.8
3.8
0
4.0
3.8
1.5
0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
KC
t
KF
t
KH
t
KL
Min
5.0
200
2.0
2.0
2.4
2.4
200MHz
Max
166MHz
Min
Max
6.0
166
2.6
2.6
150MHz
Min
6.6
150
2.6
2.6
Max
Min
7.5
133
133MHz
Max
Units
ns
MHz
ns
ns
NOTES:
1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted.
2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0.
3. This parameter is sampled.
4. Transition is measured
±500mV
from steady state voltage.
5. OE is a “Don’t Care” when a byte write enable is sampled LOW.
6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC
LOW for the required setup and hold times.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled. All other
synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when ADSC is LOW to remain enabled.
OUTPUT LOADS
Output
Z0 == 50Ω
Z0 50Ω
Parameter
Input Pulse Levels
AC TEST CONDITIONS
3.3V I/O
V
SS
to 3.0
1
1.5
1.5
2.5V I/O
V
SS
to 2.5
1
1.25
1.25
Unit
V
ns
V
V
50Ω
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
Vt
Vt
1.5V for 3.3V I/O
=
= 1.5V
Vt = 1.25V for 2.5V I/O
AC Output Load Equivalent
See figure, at left
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
