WED2DL32512V
FIG. 4
WRITE TIMING DIAGRAM
t
KHK H
t
KHK L
t
KLKH
CLK
t
SC VKH
t
KHSCX
ADSC
t
EVKH
CE
t
KHEX
t
AVKH
ADDR
A1
t
KHAX
A2
A3
A4
A5
OE
t
WVKH
KHG WX
t
KHWX
WRITE
t
DVK H
t
KHDX
DQ
D(A1)
D(A2)
D(A3)
D (A4)
D(A5)
DON’T CARE
UNDEFINED
NOTES:
1. D (A
2
) refers to output from address A
2
. D (A
2
+
1
) refers to output from the next internal burst address following A
2
.
2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the time period
prior to the byte write enable inputs being sampled.
3. Full-width WRITE can be initiated by BWE, BWa, - BWd LOW. Timing is shown assuming that the device was not enabled before entering into its sequence.
OE does not cause Q to be driven until after the following clock rising edge.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
