White Electronic Designs
I
NPUT
/O
UTPUT
F
UNCTIONAL
D
ESCRIPTION
Symbol
CK
CKE
CE#
RAS#, CAS#,
WE#
BA0, BA1
Type
Input
Input
Input
Input
Input
Signal
Pulse
Level
Pulse
Pulse
Level
WED3DL3216V
A0-12
Input
Level
DQ
Input/Output
Level
Polarity
Function
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
Active High
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
Active Low
DQM.
When sampled at the positive rising edge of the clock, CAS#, RAS# and WE# define the
Active Low
operation to be executed by the SDRAM
−
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled
at the rising clock edge.
During a Read or Write command cycle, A0-9 defines the column address (CA0-9) when
sampled at the rising edge of the clock. In addition to the row address, A10/AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,
−
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, than BA0, BA1 is used to define which bank to precharge.
−
Data Input/Output are multiplexed on the same pins
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
CC
/V
CCQ
V
IN
V
OUT
T
OPR
T
TSG
P
D
I
OS
Min
-1.0
-1.0
-1.0
-0
-55
—
—
Max
+4.6
+4.6
+4.6
+70
+125
1.5
50
Units
V
V
V
°C
°C
W
mA
* Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
