White Electronic Designs
COMMAND TRUTH TABLE
CKE
Function
Register Mode Register Set
Refresh Auto Refresh (CBR)
Entry Self Refresh
Precharge Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Device Deselect
Clock Suspend/Standby Mode
Data Write/Output Disable
Data Mask/Output Disable
Entry
Power Down Mode
Exit
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
X
X
Current
Cycle
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
CE#
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
H
H
RAS# CAS# WE#
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
H
H
H
L
L
L
L
H
H
X
X
X
X
X
X
L
H
H
L
L
H
L
L
L
H
L
H
X
X
X
X
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
BA
WED3DL3216V
A0-A10
A12, A11,
Notes
X
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
OP CODE
X
X
X
X
2
2
2
2
2
2
3
L
X
H
X
Row Address
L
Column
H
Column
L
Column
H
Column
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
5
5
6
6
NOTES:
1.
All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2.
Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3.
During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4.
During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5.
The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations,
therefore the device can’t remain in this mode longer than the Refresh period (t
REF
) of the device. One clock delay is required for mode
entry and exit.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
