White Electronic Designs
WEDPN4M72V-XB2X
TRUTH TABLE – COMMANDS AND DQM OPERATION (NOTE 1)
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) (3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) (5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register and A12 should be driven
low.
3. A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
CS#
H
L
L
L
L
L
L
L
L
–
–
RAS#
X
H
L
H
H
H
L
L
L
–
–
CAS#
X
H
H
L
L
H
H
L
L
–
–
WE#
X
H
H
H
L
L
L
H
L
–
–
DQM
X
X
X
L/H
8
L/H
8
X
X
X
X
L
H
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
–
–
I/Os
X
X
X
X
Valid
Active
X
X
X
Active
High-Z
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs
(two-clock delay).
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not
affected.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
-100
-125
-133
CAS
LATENCY = 2
≤
75
≤
100
≤
100
CAS
LATENCY = 3
≤
100
≤
125
≤
133
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until t
MRD
is met.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
