White Electronic Designs
refresh requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (t
RC
), once
every refresh period (t
REF
).
WEDPN4M72V-XB2X
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to t
RAS
and
may remain in self refresh mode for an indefinite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CK must be stable (stable clock
is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for t
XSR
,
because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
*Self refresh available in commercial and industrial temperatures only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
