WCSS0418V1P
Switching Waveforms
Write Cycle Timing
[14, 15]
t
CH
t
CYC
Burst Write
Pipelined Write
Unselected
CLK
t
ADH
t
ADS
t
CL
ADSP ignored with CE
1
inactive
ADSP
t
ADS
t
ADH
ADSC initiated write
ADSC
t
ADVS
t
ADVH
ADV
t
AS
ADV Must Be Inactive for ADSP Write
WD1
t
AH
WD2
WD3
ADD
GW
t
WS
t
WH
t
WS
CE
1
masks ADSP
t
WH
WE
t
CES
t
CEH
CE
1
t
CES
t
CEH
Unselected with CE
2
CE
2
CE
3
t
CES
t
CEH
OE
t
DS
t
DH
High-Z
Data
In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW
[1:0]
, and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
Document #: 38-05247
Page 10 of 17