W39V080APZ 参数 Datasheet PDF下载

W39V080A

Timing Waveforms for LPC Interface Mode, continued

14.7 GPI Register/Product ID Readout Timing Diagram

CLK

#RESET

#LFRAME

Memory

Read

Cycle

010Xb

1111b

1111b

1011b

Start

LAD[3:0]

0000b

Address

XXXXb

1110b

0001b

0000b

0000b

1111b

TAR

Tri-State

Sync

0000b

Data

D[3:0]

D[7:4]

TAR

Next Start

0000b

1 Clock 1 Clock

Load Address "FFBC0100(hex), or FFBXE100(hex)" in 8 Clocks

2 Clocks

1 Clock Data out 2 Clocks

1 Clock

Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved

14.8 Reset Timing Diagram

VDD

T

PRST

CLK

T

KRST

#RESET

T

RSTP

T

RST

T

RST

F

LAD[3:0]

#LFRAME

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