W681360
1. GENERAL DESCRIPTION
The W681360 is a general-purpose single channel 13–bit linear PCM CODEC with 2s complement
data format. It operates from a single +3V power supply and is available in 20-pin SOG(SOP), SSOP
and TSSOP package options. The primary function of the device is the digitization and reconstruction
of voice signals, including the band limiting and smoothing required for PCM systems. The W681360
performance is specified over the industrial temperature range of –40°C to +85°C.
The W681360 includes an on-chip precision voltage reference. The analog section is fully differential,
reducing noise and improving the power supply rejection ratio. The V
AG
reference pin allows for
decoupling of the internal circuitry that generates the reference voltage to the V
SS
power supply
ground, minimizing clock noise on the analog circuitry when external analog signals are referenced to
V
SS
.
The data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous
communications for PCM applications. The W681360 accepts eight master clock rates between
256kHz and 4.800MHz, and an on-chip pre-scaler automatically determines the division ratio for the
required internal clock.
An additional on-chip power amplifier is capable of driving 300Ω loads differentially up to a level of
3.544V peak-to-peak.
For fast evaluation a development kit (W681360DK) is available.
For fast prototyping purposes a low-cost evaluation board (W681360ES) is also available.
Applications
•
VoIP, Voice over Networks equipment
•
Digital telephone and communication
systems
•
Wireless Voice devices
•
DECT/Digital Cordless phones
•
Broadband Access Equipment
•
Bluetooth Headsets
•
Fiber-to-curb equipment
•
Enterprise phones
•
Digital Voice Recorders
2. FEATURES
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Single +3V power supply (2.7V to 5.25V)
Typical power dissipation: 9.8mW
Standby power dissipation: 3µW
Power-Down dissipation: 0.09µW
Fully-differential analog circuit design for
low noise
13-bit linear A/D & D/A conversions with 2s
complement data format
CODEC A/D and D/A filtering compliant
with ITU G.712
Eight master clock rates of 256kHz to
4.800 MHz
256KHz – 4.8MHz bit clock rates on the
serial PCM port
On-chip precision reference of 0.886 V for
a -5 dBm TLP at 600
Ω
(436mV
RMS
)
Programmable receive gain: 0 to –21dB in
3dB steps
Industrial temp. range (–40°C to +85°C)
20-pin SOG (SOP), SSOP and TSSOP as
well as a QFN-32L package
Pb-Free / RoHS package options available
-2-
Publication Release Date: September 2005
Revision A2
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