W681360
Table 7.1. When the input operational amplifier is powered down the AO pin becomes high input
impedance.
TABLE 7.1: INPUT AMPLIFIER MODES OF OPERATION
AI+
(Pin 19)
V
DD
1.2 to V
DD
-1.2
V
SS
Input Amplifier
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Input
AO (Pin 17)
AI+, AI- (Pins 19, 18)
AI- (Pin 18)
When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the
analog ground voltage V
AG
.
The output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at
the switched capacitor 3.4kHz low pass filter. Subsequently the 3.4kHz switched capacitor low pass
filter bandlimits the input signals well below 4kHz. Signals above 4kHz would be aliased at the
sampling rate of 8kHz. A high pass filter with a 200Hz cut-off frequency prevents DC coupling. All
filters are designed according to the G.712 ITU-T specification. The high-pass filter may be bypassed
depending on the logic level on the HB pin. If the high pass is removed the frequency response of the
device extends down to DC.
After filtering the signal is digitized as a 13-bit linear PCM code and fed to the PCM interface for serial
transmission at the sample rate supplied by the external frame sync FST.
7.1.1 Input Operational Amplifier Gain
The gain of the input operational amplifier can be adjusted using external resistors. For single-ended
input operation the gain is given by a simple resistive ratio.
FIGURE 7.2: INPUT OPERATIONAL AMPLIFIER GAIN – SINGLE-ENDED INPUT
Ro
AO
AI-
-
+
AI+
Ri
Vin
VAG
Gin = Ro/Ri
For differential input operation the external resistor network is more complex but the gain is expressed
in the same way. Of course, a differential input also has an inherent 6dB advantage over a
corresponding single-ended input.
-9-
Publication Release Date: September 2005
Revision A.2
WINBOND [ WINBOND ]
