W681360
7. FUNCTIONAL DESCRIPTION
W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation.
The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip
consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of
the chip provides the internal clock signals and synchronizes the CODEC sample rate with the
external frame sync frequency. The power conditioning block provides the internal power supply for
the digital and the analog section, while the voltage reference block provides a precision analog
ground voltage for the analog signal processing.
The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog
Converter (DAC) is referenced to
μ-Law
with the same bit voltage weighing about the zero crossing,
resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based
on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω.
VAG
+
-
-
+
PAO+
PAO-
PAI
13
DATA
Receive
13 bit linear
DAC
f
C
= 3400 Hz
Smoothing
Filter a
High Pass
Bypass
Buffer1
Av=1
Smoothing
Filter b
RO-
AO
-
AI-
AI+
13
DATA
Transmit
13 bit linear
ADC
f
C
= 200 Hz
High Pass
Filter
f
C
= 3400 Hz
Anti-Aliasing
Filter a
+
Anti-Aliasing
Filter b
FIGURE 7.1: THE W681360 SIGNAL PATH
7.1. Transmit Path
The first stage of the A-to-D path of the CODEC is an analog input operational
amplifier with externally configurable gain settings. A differential analog input may be
applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered
down and a single-ended input signal can be applied to either the AO pin or the AI-
pin. The input amplifier can be powered down by connecting the AI+ pin to either V
DD
or V
SS
which also determines whether AO or AI+ is selected as input according to
-8-
Publication Release Date: September 2005
Revision A.2
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