W77C32/W77C032A
SM2:
Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be
activated if the received 9
th
data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be
activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port
clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives
compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the
oscillator clock. This results in faster synchronous serial communication.
disabled.
This is the 9
th
bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as
desired.
In modes 2 and 3 this is the received 9
th
data bit. In mode 1, if SM2 = 0, RB8 is the stop bit
that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8
th
bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
Receive interrupt flag: This flag is set by hardware at the end of the 8
th
bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2 apply to this bit. This bit can be cleared only by software
REN: Receive enable: When set to 1 serial reception is enabled, otherwise reception is
TB8:
RB8:
TI:
RI:
Serial Data Buffer
Bit:
7
SBUF.7
6
SBUF.6
5
SBUF.5
4
SBUF.4
3
SBUF.3
2
SBUF.2
1
SBUF.1
0
SBUF.0
Mnemonic: SBUF
Address: 99h
SBUF.7-0: Serial data on the serial port 0 is read from or written to this location. It actually consists of
two separate internal 8-bit registers. One is the receive resister, and the other is the
transmit buffer. Any read access gets data from the receive data buffer, while write access
is to the transmit data buffer.
Port 2
Bit:
7
P2.7
Mnemonic: P2
6
P2.6
5
P2.5
4
P2.4
3
P2.3
2
P2.2
1
P2.1
0
P2.0
Address: A0h
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
address bits for accesses to external memory.
Port 4
Bit:
7
-
Mnemonic: P4
P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups.
6
-
5
-
4
-
3
P4.3
2
P4.2
1
P4.1
0
P4.0
Address: A5h
- 17 -
Publication Release Date: February 1, 2007
Revision A8
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