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WM8581SEFV 参数 Datasheet PDF下载

WM8581SEFV图片预览
型号: WM8581SEFV
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 94 页 / 1024 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8581
TERMINOLOGY
1.
2.
Product Preview
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N
@ -60dB= -32dB, DR= 92dB).
THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3.
4.
5.
6.
MASTER CLOCK TIMING
t
MCLKL
ADCMCLK/
MCLK
t
MCLKY
t
MCLKH
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T
A
= +25
o
C
PARAMETER
System Clock Timing Information
ADCMCLK and MCLK System clock
pulse width high
ADCMCLK and MCLK System clock
pulse width low
ADCMCLK and MCLK System clock
cycle time
ADCMCLK and MCLK Duty cycle
SYMBOL
t
MCLKH
t
MCLKL
t
MCLKY
TEST CONDITIONS
MIN
11
11
28
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
Table 3 Master Clock Timing Requirements
w
PP Rev 1.0 March 2006
12