WM8728
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Product Preview
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
Master Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
SYMBOL
t
MCLKH
t
MCLKL
t
MCLKY
TEST CONDITIONS
MIN
13
13
26
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
DIGITAL AUDIO INTERFACE
t
BCH
BCKIN
t
BCY
t
BCL
LRCIN
t
DS
DIN
t
DH
t
LRH
t
LRSU
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
LRCIN hold time from
BCKIN rising edge
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
SYMBOL
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DS
t
DH
TEST CONDITIONS
MIN
40
16
16
8
8
8
8
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Audio Data Input Timing Information
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
