WM8728
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MPU 3-WIRE INTERFACE TIMING
CSBIWL
t
CSSU
t
CSSH
t
CSL
LATI2S
t
SCY
t
SCH
SCKDSD
t
SCL
t
SCS
t
CSS
t
CSH
SDIDEM
t
DSU
t
DHO
LSB
Figure 5 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SCKDSD rising edge to LATI2S
rising edge
SCKDSD pulse cycle time
SCKDSD pulse width low
SCKDSD pulse width high
SDIDEM to SCKDSD set-up
time
SCKDSD to SDIDEM hold time
LATI2S pulse width low
LATI2S pulse width high
LATI2S rising to SCKDSD rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time
SYMBOL
t
SCS
t
SCY
t
SCL
t
SCH
t
DSU
t
DHO
t
CSL
t
CSH
t
CSS
t
CSSU
t
CSSH
TEST CONDITIONS
MIN
40
80
20
20
20
20
20
20
20
20
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Program Register Input Information
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
