Advanced Information
WM8753L
Test Conditions
DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode
fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MODE/GPIO3 and CSB/GPIO5 to AVDD
and DCVDD power-up setup time
tpusetup
tpuhold
tdbpu
100
1
us
ms
us
AVDD and DCVDD to MODE/GPIO3 and
CSB/GPIO5 hold time
DBVDD powerup to DCVDD or AVDD
powerup
0
Note:
1. DBVDD must be supplied before or at same time as either DCVDD or AVDD to ensure MODE and CSB are defined
internally when power on reset is released
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC,
Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRC / VXFS propagation delay from BCLK / VXCLK falling
edge
tDL
10
10
ns
ns
ADCDAT / VXDOUT propagation delay from BCLK / VXCLK
falling edge
tDDA
DACDAT / VXDIN setup time to BCLK / VXCLK rising edge
DACDAT / VXDIN hold time from BCLK / VXCLK rising edge
tDST
tDHT
10
10
ns
ns
AI Rev 3.1 June 2004
14
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
