WM8753L
Advanced Information
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC,
Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK / VXCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
BCLK / VXCLK pulse width high
BCLK / VXCLK pulse width low
LRC / VXFS set-up time to BCLK / VXCLK rising edge
LRC / VXFS hold time from BCLK / VXCLK rising edge
DACDAT / VXDIN hold time from BCLK / VXCLK rising
edge
ADCDAT / VXDOUT propagation delay from BCLK /
VXCLK falling edge
tDD
10
ns
Note:
1. BCLK / VXCLK period should always be greater than or equal to MCLK / VXCLK period.
AI Rev 3.1 June 2004
15
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
