Advanced Information
WM8753L
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
SDOUT
LSB
tDD
Note:
SDOUT is not an external pin. For data readback SDOUT may be selected to be ADCDAT, GP1, GP2,
GPIO3 or GPIO4
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC,
Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tDD
80
200
80
80
40
40
40
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
SCLK falling to SDOUT propagation delay
Pulse width of spikes that will be suppressed
10
tps
5
AI Rev 3.1 June 2004
16
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
