WM8768
INTERNAL POWER ON RESET CIRCUIT
Production Data
Figure 7 Internal Power on Reset Circuit Schematic
The WM8768 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset
the digital logic into a default state after power up. The POR circuit is powered from DVDD and
monitors DVDD. It asserts PORB low if DVDD is below a minimum threshold.
Figure 8 Typical Power-Up Sequence
Figure 8 shows a typical power-up sequence. When DVDD goes above the minimum threshold,
Vpord, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held
in reset. In this condition, all writes to the control interface are ignored. When DVDD rises to
Vpor_on, PORB is released high and all registers are in their default state and writes to the control
interface may take place.
On power down, PORB is asserted low whenever DVDD drops below the minimum threshold
Vpor_off.
SYMBOL
V
pord
V
por_on
V
por_off
MIN
0.3
1.3
1.3
TYP
0.5
1.7
1.7
MAX
0.8
2.0
2.0
UNIT
V
V
V
Table 5 Typical POR Operation (typical values, not tested)
w
PD Rev 4.1 March 2005
12
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
