WM8768
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Production Data
Figure 1 DAC Master Clock Timing Requirements
Test Conditions
o
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T
A
= +25 C, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be
accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically
powered up, but a write to the volume update register bit is required to restore the correct volume settings.
After MCLK stopped
After MCLK re-started
t
MCLKH
t
MCLKL
t
MCLKY
11
11
28
40:60
2
0.5
1000
60:40
10
1
Us
MCLK
cycle
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
WM8768
DAC
LRCLK
DIN1/2/3/4
4
DSP/
DECODER
Figure 2 Audio Interface - Master Mode
w
PD Rev 4.1 March 2005
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
