Production Data
WM8768
BCLK
(Output)
t
DL
LRCLK
(Output)
DIN1/2/3/4
t
DST
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
o
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T
A
= +25 C, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
LRCLK propagation delay
from BCLK falling edge
DIN1/2/3/4 setup time to
BCLK rising edge
DIN1/2/3/4 hold time from
BCLK rising edge
SYMBOL
t
DL
t
DST
t
DHT
TEST CONDITIONS
MIN
0
10
10
TYP
MAX
10
UNIT
ns
ns
ns
t
DHT
Audio Data Input Timing Information
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8768
DAC
LRCLK
DIN1/2/3/4
4
DSP/
DECODER
Figure 4 Audio Interface – Slave Mode
w
PD Rev 4.1 March 2005
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
