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WM8782SEDS/R 参数 Datasheet PDF下载

WM8782SEDS/R图片预览
型号: WM8782SEDS/R
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声ADC [24-Bit, 192kHz Stereo ADC]
分类和应用: 商用集成电路光电二极管
文件页数/大小: 21 页 / 237 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8782
AUDIO DATA FORMATS
Production Data
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length)
In I
2
S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 9 I
2
S Audio Interface (assuming n-bit word length)
w
PD, August 2006, Rev 4.2
12