Production Data
WM8782
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
Table 3 Digital Audio Data Timing - Slave Mode
Note:
LRCLK should be synchronous with MCLK, although the WM8782 interface is tolerant of phase variations or jitter on these
signals.
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DD
50
20
20
10
10
0
10
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
TYP
MAX
UNIT
w
PD, August 2006, Rev 4.2
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
