X25128
be low when HOLD is first pulled low and SCK must
also be low when HOLD is released.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The HOLD input may be tied high either directly to V
CC
or tied to V through a resistor.
CC
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
Operational Notes
The X25128 powers-up in the following state:
• CS must come high at the proper clock count in
order to start a write cycle.
• The device is in the low power standby state.
• A high to low transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
2
Figure 1. Read E PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3091 FM F03
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3091 FM F04
5
XICOR [ XICOR INC. ]
