X4643/5 – Preliminary Information
standard V
TRIP
thresholds are available, however,
Xicor’s unique circuits allow the threshold to be
reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher
precision.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S
0
S
1
RESET/RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
8 Pin TSSOP
WP
V
CC
S
0
S
1
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RESET/RESET
PIN FUNCTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
0
S
1
Device Select Input
Device Select Input
Function
RESET
/
RESET
Reset Output
. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain
active until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes
active on power up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the de-
vice. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
4
5
6
7
V
SS
SDA
6
7
8
8
1
2
SCL
WP
V
CC
REV 1.26 4/30/02
www.xicor.com
Characteristics subject to change without notice.
2 of 22
XICOR [ XICOR INC. ]
