XCR3256XL 256 Macrocell CPLD
R
Timing Model
The XPLA3 architecture follows a simple timing model that
allows deterministic timing in design and redesign. The
basic timing model is shown in
One key feature of
the XPLA3 CPLD is the ability to have up to 48 product term
inputs into a single macrocell and maintain consistent tim-
ing. This is achieved through the use of a fully populated
PLA (Programmable AND Programmable OR Array) which
also has the ability to share product terms and only use the
required amount of product terms per macrocell. There is a
fast path (T
LOGI1
) into the macrocell which is used if there is
a single product term. The T
LOGI2
path is used for multiple
product term timing. For optimization of logic, the XPLA3
CPLD architecture includes a Fold-back NAND path
(T
LOGI3
). There is a fast input path to each macrocell if used
as an Input Register (T
FIN
). XPLA3 also includes universal
control terms (T
UDA
) that can be used for synchronization of
the macrocell registers in different logic blocks. There is
also slew rate control and output enable control on a per
macrocell basis.
T
F
T
IN
T
LOGI1,2
DLT
CE
Q
T
OUT
T
EN
T
SLEW
T
FIN
T
GCK
T
LOGI3
T
UDA
S/R
DS017_02_042800
Figure 2:
XPLA3 Timing Model
4
1-800-255-7778
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
XILINX [ XILINX, INC ]
