0
R
Virtex™ 2.5 V
Field Programmable Gate Arrays
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3
DS003-1 (v2.5 ) April 2, 2001
Product Specification
Features
•
Fast, high-density Field-Programmable Gate Arrays
•
•
Supported by FPGA Foundation™ and Alliance
Development Systems
-
-
-
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Densities from 50k to 1M system gates
System performance up to 200 MHz
66-MHz PCI Compliant
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Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
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Wide selection of PC and workstation platforms
Hot-swappable for Compact PCI
SRAM-based in-system configuration
•
•
Multi-standard SelectIO™ interfaces
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Unlimited re-programmability
Four programming modes
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16 high-performance interface standards
Connects directly to ZBTRAM devices
•
•
0.22 m 5-layer metal process
100% factory tested
Built-in clock-management circuitry
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Four dedicated delay-locked loops (DLLs) for
advanced clock control
Description
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Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 m CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in Table 1.
•
•
Hierarchical memory system
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-
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LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
-
-
-
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Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
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-
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IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Table 1: Virtex Field-Programmable Gate Array Family Members
Maximum
Block RAM
Bits
Maximum
SelectRAM+™ Bits
Device
System Gates
CLB Array
Logic Cells
Available I/O
XCV50
57,906
16x24
1,728
180
180
260
284
316
404
512
512
512
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
108,904
20x30
2,700
164,674
24x36
3,888
236,666
28x42
5,292
322,970
32x48
6,912
468,252
40x60
10,800
15,552
21,168
27,648
661,111
48x72
888,439
56x84
1,124,022
64x96
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001
Product Specification
www.xilinx.com
1-800-255-7778
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