MT8980D
Data Sheet
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
44 PIN PLCC
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
40
44
DIP PLCC
Name
Description
1
2
DTA
Data Acknowledgement (Open Drain Output).
This is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909
Ω,
1/4W, resistor is recommended to be used as a pullup.
2-4
5-9
10
11
3-5
7-11
12
13
STi0-
ST-BUS Input 0 to 2 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS input streams.
STi2
STi3-
ST-BUS Input 3 to 7 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS input streams.
STi7
V
DD
F0i
Power Input.
Positive Supply.
Framing 0-Type (Input).
This is the input for the frame synchronization pulse for the 2048 kbit/s
ST-BUS streams. A low on this input causes the internal counter to reset on the next negative
transition of C4i.
4.096 MHz Clock (Input).
ST-BUS bit cell boundaries lie on the alternate falling edges of this clock.
12
14
C4i
13-15 15-17 A0-A2
Address 0 to 2 (Inputs).
These are the inputs for the address lines on the microprocessor interface.
16-18 19-21 A3-A5
Address 3 to 5 (Inputs).
These are the inputs for the address lines on the microprocessor interface.
19
20
21
22
23
24
DS
R/W
CS
Data Strobe (Input).
This is the input for the active high data strobe on the microprocessor interface.
Read or Write (Input).
This is the input for the read/write signal on the microprocessor interface -
high for read, low for write.
Chip Select (Input).
This is the input for the active low chip select on the microprocessor interface
2
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
