MT8980D
(unused)
Mode
Control
Bits
Memory
Select
Bits
Stream
Address
Bits
Data Sheet
7
6
5
4
3
2
1
0
BIT
7
NAME
DESCRIPTION
Split Memory
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory
Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify
the memory for subsequent operations. In either case, the Stream Address Bits select the subsection
of the memory which is made available.
Message
Mode
(unused)
Memory
Select Bits
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
When 1, the contents of the Connection Memory Low are output on the Serial Output streams
except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine
what is output.
6
5
4-3
2-0
Stream
The number expressed in binary notation on these bits refers to the input or output ST-BUS stream
Address Bits
which corresponds to the subsection of memory made accessible for subsequent operations.
Figure 4 - Control Register Bits
Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,
the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the
ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,
regardless of the actual values.
If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally
(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the
corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the
bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-
BUS input stream and channel where the byte is to be found (see Fig. 6).
If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,
then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the
Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output
stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).
Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for
delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS
streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output
synchronously with ST-BUS channel 8 bits 7-0.
6
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
