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ZL30416GGG2 参数 Datasheet PDF下载

ZL30416GGG2图片预览
型号: ZL30416GGG2
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH时钟倍频PLL [SONET/SDH Clock Multiplier PLL]
分类和应用: 时钟
文件页数/大小: 22 页 / 872 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30416  
Data Sheet  
4.2.2 Interfacing to OC-CLKo Output  
4.2.2.1 LVPECL to LVPECL Interface  
The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and  
19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω  
termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The  
terminating resistors should be placed close to the LVPECL receiver.  
Typical resistor values: R1 = 127 , R2 =82.5 Ω  
+3.3 V  
0.1 uF  
VCC=+3.3 V  
R1  
ZL30416  
VCC  
LVPECL  
Receiver  
R1  
R2  
Z=50 Ω  
Z=50 Ω  
LVPECL  
Driver  
OC-CLKoP  
OC-CLKoN  
R2  
GND  
Figure 8 - LVPECL to LVPECL Interface  
10  
Zarlink Semiconductor Inc.