ZL38065
1.0
Device Overview
Data Sheet
The ZL38065 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-
Back configurations. In
Normal configuration,
a group of echo cancellers provides two channels of 64 ms echo
cancellation, which run independently on different channels. In
Extended Delay
configuration, a group of echo
cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In
Back-to-Back
configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64 ms echo cancellation.
Each echo canceller contains the following main elements (see Figure 4).
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Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat instability in very low ERL environments
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
+9 to -12 dB level adjusters at all signal ports
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder compatible with
µ/A-Law
ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL38065 has four functional states:
Mute, Bypass, Disable Adaptation
and
Enable
Adaptation.
These are explained in section 3.0, “Echo Canceller Functional States“.
Sin
(channel N)
µ/A-Law/
Linear
+9 to -12 dB
Level Adjust
Disable Tone
Detector
Offset
Null
Σ
-
Adaptive
Filter
Non-Linear
Processor
+9 to -12 dB
Level Adjust
Linear/
µ/A-Law
Sout
(channel N)
Control
Microprocessor
Interface
Double - Talk
Detector
MuteR
MuteS
Path Change
Detector
Disable Tone
Detector
µ/A-Law/
Linear
ST-BUS
PORT1
ST-BUS
PORT2
Instability
Detector
Narrow-Band
Detector
Linear/
µ/A-Law
+9 to -12 dB
Level Adjust
+9 to -12 dB
Level Adjust
Rout
(channel N)
Offset
Null
Rin
(channel N)
Echo Canceller (N), where 0 < N < 31
Programmable Bypass
Figure 4 - Functional Block Diagram
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
